The present invention relates to a system for switching multiple virtual spaces adapted to be used with a digital electronic computer of a virtual memory system.
In the virtual memory system a virtual space having a capacity exceeding that of a memory actually provided can be embodied. In contrast to the virtual space, a space realized on a memory is termed a real space.
An address translating table is provided for translating a virtual space to a real space. The address translating table is provided on a memory, with the result that it takes much time if reference is made to the address translating table for each reference to the virtual space.
In this respect, attention is paid to the fact that reference is often made to some concentrated portion of the virtual space if taking into account a short time in carrying out a program. An address set is made of an address of the virtual space, i.e., a virtual address and an address of the real space corresponding thereto, i.e., a real address. Then, the address set to which reference has been lately made is stored on a high speed memory such as a high speed associative memory provided separately from the above-mentioned memory. Thus, reference is made first to the high speed memory, and next to the address translating table if address set corresponding to the referred virtual address can not be found in the high speed memory.
Further, a multiple virtual spaces can be embodied without being restricted to one virtual space, and a plurality of address translating tables are provided which correspond to the respective virtual spaces.
On the other hand, software controlling the digital electronic computer may be divided into a control program, compiler, user program, and the like. In general, the user program is carried out in multi-programming. In this case, the respective user programs are partitioned in a short time and switched (hereinafter referred to as a task switch) for parallel excecution.
The virtual spaces are switched in succession for each task switch in a state where one user program occupies one of the virtual spaces and a plurality of user programs are carried out on multiple virtual spaces in multi-programming. Conventionally, in this case, the address translating tables provided in correspondence with the respective virtual spaces are switched simultaneously with the task switch, and further all the address sets of the virtual and real addresses in the high speed memory provided in common are made invalid. The reason is that the switching of the address translating table otherwise makes nonsense.
Particularly explaining, the above-mentioned high speed memory is controlled as follows:
1. If the address set having the referred virtual address is registered in the high speed memory, then the real address corresponding to the referred virtual address is extracted for prompt reference to the real space.
2. If the address set having the referred virtual address is not registered in the high speed memory, then reference is made to the address translating table to search the corresponding real address so that this address set may be registered in the high speed memory. At this time, if the high speed memory has no place for registration of this new address set because of full registration therein, one of the address sets previously registered therein is erased in accordance with a predetermined algorithm to provide a place for registration of the new address set.
The fact that all of the address sets in the high speed memory are made invalid upon the task switch as mentioned earlier means an increase in the above operation (2). In other words, the reference to the address translation table increases each time of the task switch with the result that much time is required for reference, thereby preventing the high speed operation of the digital electronic computer.